HyperTransport™ System Architecture

Example 9: WrSized Request Crosses A Bridge

Problem: Device 2 (UnitID2) in Figure 7-11 on page 189 targets main memory with a non-posted sized (dword) write of one dword. The non-isochronous transaction must cross a HyperTransport-HyperTransport bridge; there is no coherency requirement.

Figure 7-11. Sized (Dword) Write Transaction Must Cross A Bridge

Example 9: Request Packet On Bus 1

(Refer to [1] in Figure 7-11 on page 189)

Command[5:0] Field (Byte 0, Bit 5:0)

This is the sized write (WrSized) command code. Assume dword (bit 2) is enabled; the posted (bit 5), Isoc (bit 1), and coherency (bit 0) bits are all disabled (0). This indicates a non-isochronous, ...