February 2003
Intermediate to advanced
592 pages
11h 47m
English
This section defines the timing parameters for CAD[n:0], CTL, and CLK[m:0].
The HyperTransport link uses a simple timing methodology that accounts for simultaneous worst case combinations of uncertainties. This timing methodology attempts to cover all cases that could occur in operational systems, and is defined to provide zero additional margin. This means that board designers and designers of device transmitter and receiver interfaces must meet specification requirements over all process, voltage, and temperature corner cases.
The maximum skew allowed by the output driver between the true signal and its differential complement is defined as TODIFF. Figure 14-10 on page 380 illustrates ...
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