HyperTransport™ System Architecture

DownStream HT to Expansion Bus Memory Mapping

Downstream memory transactions may be accomplished solely on the basis of mapping registers defined by the bus architecture (e.g. PCI), or may be aided by the Address Remapping Capability block registers when the HT addresses are outside the range of the expansion bus memory address range. Because HT defines a large range of address space for mapping memory and MMIO locations (00_0000_0000h-FC_FFFF_FFFFh), its address space may extend beyond the address range of the secondary bus.

Downstream Memory Access Without Remapping

The first example represents the simple case where no remapping of memory addresses is required. This example assumes that the processor memory space is directly mapped to HT address ...