46 IBM ^ zSeries 990 Technical Guide
Extended Translation Facility
The Extended Translation Facility adds 10 instructions to the zSeries instruction set. They
enhance the performance for data conversion operations for data encoded in Unicode,
making applications enabled for Unicode and/or Globalization more efficient. These data
encoding formats are used in Web Services, Grid, and on demand environments where XML
and SOAP technologies are used. The High Level Assembler will be the first to support the
Extended Translation Facility instructions.
2.2.4 Processor Unit functions
One of the key components of the z990 server is the Processor Unit (PU). This is the
microprocessor chip where instructions are executed and the related data resides. The
instructions and the data are stored in the PU’s high-speed buffer, called the Level 1 cache.
Each PU has its own 512 KB Level 1 cache, split into 256 KB for data and 256 KB for
instructions.
The L1 cache is designed as a store-through cache, which means that altered data is
synchronously stored into the next level, the L2 cache. Each PU has multiple processors
inside and instructions are executed twice, asynchronously, on both processors.
This asymmetric mirroring of instruction execution runs one cycle behind the actual operation.
This allows the circuitry on the chip to be optimized for performance and does not
compromise the simplified error detection process that is inherent to a mirrored execution unit
design.
One or two Processor Units are contained on one processor chip. All PUs of a z990 server
reside in a MultiChip Module. An MCM holds 12 PUs, of which eight are available for
customer use, two are SAPs, and two are spares. Up to four MCMs, each contained in a
book, may be available in one z990 server.
This approach allows a z990 server to have more PUs than required for a given initial
configuration. This is a key point of the z990 design and is the foundation for the configuration
flexibility and scalability of a single server.
All PUs in a z990 server are physically identical, but at initialization time PUs can be
characterized to specific functions: CP, IFL, ICF, zAAP, or SAP. The function assigned to a PU
is set by the Licensed Internal Code loaded when the system is initialized (Power-on Reset)
and the PU is “characterized”. Only characterized PUs have a designated function;
non-characterized PUs are considered spares.
This design brings an outstanding flexibility to the z990 server, as any PU can assume any
available characterization. This also plays an essential role in z990 system availability, as
these PU assignments can be done dynamically, with no server outage, allowing:
򐂰 Concurrent upgrades
Except on a fully configured model, concurrent upgrades can be done by the Licensed
Internal Code, which assigns a PU function to a previously non-characterized PU. Within
the book boundary or boundary of multiple books, no hardware changes are required, and
the upgrade can be done via Capacity Upgrade on Demand (CUoD), Customer Initiated
Upgrade (CIU), On/Off Capacity on Demand (On/Off CoD), or Capacity BackUp (CBU).
More information about capacity upgrades is provided in 8.1, “Concurrent upgrades” on
page 188.

Get IBM eServer zSeries 990 Technical Guide now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.