IBM eServer zSeries 990 Technical Guide

Chapter 2. System structure and design 53

Table 2-3 PU chip allocation

򐂰 On a single-book configuration, model A08:

– When a PU failure occurs on a dual-core chip, the two standard spares PUs are used

to recover the failing chip, even though only one of the PUs has failed.

– When a failure occurs on a PU on a single-core chip, one standard spare PU is used.

The system does not issue an RSF call in either of the above circumstances.

When a non-characterized PU is used as a spare, in case the system has run out of the

standard spares, or when all PUs have been assigned and no non-characterized PU

remains available, an RSF call occurs to request a book repair.

򐂰 On a multi-book configuration, models B16, C24, or D32:

– In a first step, the standard spare PUs of the MCM where the failing PU resides is

assigned as spare, in the same manner as for a one-book system.

– In a second step, when there are not enough spares in the book with the failing PU,

non-characterized PUs in other books are used for sparing. When “cross-book” sparing

occurs, the book closest to the one with the failing PU will be used.

For example, if a PU failure in Book-1 cannot be solved within locally, spares in Book-2

or Book-0 are then selected. When no spares are available in any adjacent book,

Book-3 is approached for a spare PU.

2.2.5 Memory design

As for PUs and the I/O subsystem designs, the z990 memory design equally provides great

flexibility and high availability, allowing:

򐂰 Concurrent Memory upgrades (except when the physically installed capacity is reached.)

The z990 servers may have more physically installed memory than the initial available

capacity. Memory upgrades within the physically installed capacity can be done

concurrently by the Licensed Internal Code, and no hardware changes are required.

Concurrent memory upgrades can be done via Capacity Upgrade on Demand or

Customer Initiated Upgrade. Note that memory upgrades

cannot be done via Capacity

BackUp (CBU); see Table 8-1 on page 190 for more information.

Core Core X = CP, IFL, ICF, or zAAP

Single core

0- X -

2- X -

4- X -

6- X -

Dual core 8 9 X Spare

A B X Spare

C D X SAP

E F X SAP