2.1 The IBM Power10 processor2.1.1 Power10 processor overview2.1.2 Dual-chip modules for Power E1050 server2.1.3 Power10 processor core2.1.4 Simultaneous multithreading2.1.5 Matrix Math Acceleration AI workload acceleration2.1.6 Power10 compatibility modes2.1.7 Processor module options2.1.8 Processor activations2.1.9 On-chip L3 cache and intelligent caching2.1.10 Nest accelerator2.1.11 SMP interconnect and accelerator interface2.1.12 Power and performance management2.1.13 Comparing Power10, Power9, and Power8 processors2.2 Memory subsystem2.2.1 Open Memory Interface2.2.2 Differential Dual Inline Memory Module2.2.3 Memory activations2.2.4 Memory placement rules2.2.5 Pervasive memory encryption2.2.6 Active Memory Mirroring2.3 Internal I/O subsystem2.3.1 PCIe adapter slot details2.3.2 I/O Blind-Swap Cassettes2.3.3 Non-volatile Memory Express bays2.3.4 Attachment of I/O-drawers2.3.5 System ports2.4 Component summary per processor socket configuration2.5 The enterprise Baseboard Management Controller2.5.1 Managing the system by using the ASMI GUI2.5.2 Managing the system by using DMTF Redfish2.5.3 Managing the system by using the IPMI