IBM TotalStorage DS6000 Series: Performance Monitoring and Tuning

22 IBM TotalStorage DS6000 Series: Performance Monitoring and Tuning

structure and algorithms that the DS6000 uses, are factors that improve the I/O performance.

The significance of this benefit will mostly be determined by the type of workload that is run.

In the DS6000 there is 4 GB of fixed cache. This cache is divided between the two servers of

the DS6000, giving the servers their own non-shared cache.

To protect the data that is written during the I/O operations, the DS6000 stores two copies of

the data: One in the cache and another in its persistent memory.

2.5.2 Persistent memory

The persistent memory is used to store a second copy of the written data to ensure data

integrity should there be a power failure or a server failure and the cache copy would be lost.

The persistent memory of server 0 is located in server 1 of the DS6000, and the persistent

memory of server 1 is located in server 0 as depicted Figure 2-3. In this way, in the event of a

server failure, the updated data of the failed server will be in the persistent memory of the

surviving server. This write data can then be destaged to the disk arrays. At the same time,

the surviving server will start to use its own persistent memory for all write data, ensuring that

write data is still maintained. This ensures that no data is lost even in the event of a

component failure.

Figure 2-3 Persistent memory

2.5.3 Cache algorithms

Most, if not all, high-end disk systems have internal cache integrated into the system design,

and some amount of system cache is required for operation. Over time, cache sizes have

dramatically increased, but the ratio of cache size to system disk capacity has remained

nearly the same.

The DS6000 uses the patent-pending

Adaptive Replacement Cache (ARC) algorithm,

developed by IBM Storage Development in partnership with IBM Research. It is a self-tuning,

self-optimizing solution for a wide range of workloads with a varying mix of sequential and

random I/O streams. For a detailed description of ARC, see N. Megiddo and D. S. Modha,

“Outperforming LRU with an adaptive replacement cache algorithm,” IEEE Computer, vol. 37,

no. 4, pp. 58–65, 2004.

ARC basically attempts to determine four things:

Cache

memory

for

Server 0

NVS

for

Server1

NVS

for

Server 0

Cache

memory

for

Server 0

Server 0

Server 0 Server 1