The G4e’s AltiVec implementation is the strongest part of its design. With four fully pipelined vector processing units, it has plenty of hardware to go around. As a brief recap from the last chapter, here’s a breakdown of the G4e’s four AltiVec units:
vector permute unit (VPU)
vector simple integer unit (VSIU)
vector complex integer unit (VCIU)
vector floating-point unit (VFPU)
All of this vector execution hardware is tied to a generous register file that consists of thirty-two 128-bit architectural registers and sixteen additional vector rename registers. Furthermore, each of the units is attached to a four-entry vector issue queue that can issue two vector ops per cycle to any of the four vector units.