Integrated Circuit Design for Radiation Environments

7 Radiation Semiconductor Process and Layout Solutions

7.1 Introduction

Solutions to improve radiation tolerance are achievable by providing semiconductor processes that lessen the sensitivity to ionizing particles. This chapter will focus on semiconductor process development and layout solutions that minimize both soft error rate (SER) and latchup. Technologies that provide immunity from ionizing particles are known as “radiation hardened” technologies. Radiation tolerance can be natural to the structural features of the devices in the technology. Radiation sensitivity can also be addressed using layout solutions as well. In this chapter, both radiation hardened technology and layout solutions are discussed.

The chapter will discuss silicon on insulator (SOI), silicon on sapphire (SOS), silicon on diamond (SOD), and other radiation hardening techniques in bulk complementary metal oxide semiconductor (CMOS). Bulk CMOS radiation hardening can include solutions in the substrate, epitaxial region, wells, isolation, and buried layers. The chapter will examine radiation‐hardened semiconductor technologies. The chapter will also discuss SOI, SOS, SOD, and other radiation hardening techniques in bulk CMOS [1–58].

7.2 Substrate Hardened Technologies

Radiation hardening can be addressed by the choice of the substrate used in the technology. In radiation environment, the substrate plays a key role in interaction between the incoming ionized particle and the wafer that supports ...