Integrated Circuit Design for Radiation Environments

8 Single‐Event Upset Circuit Solutions

8.1 Introduction

Single‐event upsets can be minimized with semiconductor process solutions, as well as circuit solutions. Single‐event upset solutions are dependent on the semiconductor technology type, circuits, and system. Figure 8.1 highlights the type of circuits that are prone to single‐event upsets.

Figure 8.1 Types of circuits sensitive to single‐event upsets (SEU).

8.2 CMOS DRAM SEU Circuit Solutions

Single‐event upsets occur in dynamic read access memory (DRAM) [1]. The rate of failure of the single‐event upsets is also referred to as the soft error rate (SER). A single‐event upset (SEU) from an ionized particle can occur from alpha particles, muons, protons, neutrons, and heavy ions [1–24]. Figure 8.2 highlights the factors that influence the SER in a DRAM. The SER is a function of the following:

• DRAM cell size
• DRAM cell stored charge
• DRAM technology type
• DRAM technology generation

Figure 8.2 CMOS DRAM features that influence SEU.

Figure 8.3 shows an example of a CMOS DRAM cell. The DRAM cell stores charge in a trench capacitor used in a 4‐Mb DRAM technology, known as a substrate plate trench (SPT) DRAM cell [4–6]. The advantage of a trench capacitor cell is that a large amount of charge can be stored ...