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Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers by Rezaur Rahman

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CHAPTER 6

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Xeon Phi PCIe Bus Data Transfer and Power Management

This chapter looks at how the coprocessor is configured in a Xeon-based server platform and communicates with the host. It will also look at the power management capabilities built into the coprocessor to help reduce power consumption while idle. Figure 6-1 shows a system with multiple Intel Xeon Phi and two socket Intel Xeon processors. The coprocessor connects to the host using PCI Express 2.0 interface x16 lanes. Data transfer between the host memory and the GDDR memory can be through programmed I/O or through direct memory access (DMA) transfer. In order to optimize the data transfer ...

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