A VHDL program is written in a text file and has the extension “.vhd” (sometimes, “.vhdl”). VHDL is not case sensitive. Every VHDL program has associated with it an entity. The interface to the outside world (through pins) is described in this section. Every entity has associated with it an architecture. The architecture describes the behavior or structure of the design coded in the VHDL program. The design units of VHDL, apart from entity and architecture, are package, package body, and configuration. These are not required to be present in every VHDL design, but designers use them for a better coding style and for convenience. Each design unit of a VHDL design can be in a separate file. It is not required that an entity and the corresponding architecture be described in the same file. It is important to note that a single IC can be built from many VHDL files. For example, a design may be built hierarchically. A multiplier may be built from full-adders, which in turn may be built from half-adders. One could write VHDL programs for the half-adder, put two instances (copies) of the half-adder in another VHDL program to build a full-adder, and write a third program to put full-adders together to make a multiplier. This is an example of hierarchical design (bottom-up design). VHDL programming is not case sensitive; however, to identify the keywords of a VHDL program, they will be written in lowercase boldface letters.