Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

4.1. Overview of Itanium Instruction Formats

The Itanium architecture specifies 128 general-purpose registers, Gr₀ … Gr₁₂₇, significantly more than most RISC designs. Since 7 bits are required for the 128 different codes for the register identities and since many CPU operations in RISC-like architectures require three register addresses, register addressing alone consumes 21 bits within a hypothetical 32-bit instruction. If the Itanium design had used the prevalent instruction size of 32 bits, only 11 bits would have been left for the opcode and any other requirements in the design of an instruction set.

The trade-off between addressing a large bank of registers and having enough bits for opcode and parameter encoding in the instruction set is ...