Juniper MX Series

Trio

Juniper Networks prides itself on creating custom silicon and making history with silicon firsts. Trio is the latest milestone:

• 1998: First separation of control and data plane

• 1998: First implementation of IPv4, IPv6, and MPLS in silicon

• 2000: First line-rate 10 Gbps forwarding engine

• 2004: First multi-chassis router

• 2005: First line-rate 40 Gbps forwarding engine

• 2007: First 160 Gbps firewall

• 2009: Next generation silicon: Trio

• 2010: First 130 Gbps PFE; next generation Trio

Trio is a fundamental technology asset for Juniper that combines three major components: bandwidth scale, services scale, and subscriber scale. Trio was designed from the ground up to support high-density, line-rate 10G and 100G ports. Inline services such as IPFLOW, NAT, GRE, and BFD offer a higher level of quality of experience without requiring an additional services card. Trio offers massive subscriber scale in terms of logical interfaces, IPv4 and IPv6 routes, and hierarchical queuing.

Figure 1-19. Juniper Trio scale: Services, bandwidth, and subscribers.

Trio is built upon a Network Instruction Set Processor (NISP). The key differentiator is that Trio has the performance of a traditional ASIC, but the flexibility of a field-programmable gate array (FPGA) by allowing the installation of new features via software. Here is just an example of the inline services available with the Trio chipset:

• Tunnel encapsulation ...