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JUNOS High Availability by Orin Blomberg, Senad Palislamovic, Kieran Milne, James Sonderegger

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Packet Flows

From a high availability perspective, the divided architecture affects how packets flow through the different equipment. As with the hardware, the way packets flow through the network varies slightly across the equipment lines. It is important to understand how packets are passed through the components to fully realize what impact a component failure might have on the high availability of an individual piece of equipment and of the entire network.

Packet flows throughout the Juniper equipment line are similar, with differences that are primarily the result of hardware size and scalability. At the enterprise routing level, J Series packets travel through a virtualized environment mimicking the hardware of the larger pieces of equipment. Beginning with the M Series (the M7i and M10i) and extending into the entire Juniper router and switch product line, packet flow depends on ASICs to perform very specialized tasks, such as Layer 2 processing, data buffering, and most importantly, longest-prefix match lookup and packet header processing.

In all Juniper architecture, packet processing is not performed on the packet itself; instead, the routers use a copy of the key information within the IP header. As each incoming packet is processed, the packet is split into 64-byte J-cells, which are stored in the RAM of the forwarding engine. The key information from the IP header, as well as local information, such as the incoming interface, is copied into a Juniper-specific cell of ...

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