Large Scale Network-Centric Distributed Systems

1

A Reconfigurable On-Chip Interconnection Network for Large Multicore Systems

Mehdi Modarressi and Hamid Sarbazi-Azad

Contents

1.1 Introduction

1.1.1 Multicore and Many-Core Era

1.1.2 On-Chip Communication

1.1.3 Conventional Communication Mechanisms

1.1.4 Network-on-Chip

1.1.5 NoC Topology Customization

1.1.6 NoCs and Topology Reconfigurations

1.1.7 Reconfigurations Policy

1.2 Topology and Reconfiguration

1.3 The Proposed NoC Architecture

1.3.1 Baseline Reconfigurable NoC

1.3.2 Generalized Reconfigurable NoC

1.4 Energy and Performance-Aware Mapping

1.4.1 The Design Procedure for the Baseline Reconfigurable NoC

1.4.1.1 Core-to-Network Mapping

1.4.1.2 Topology and Route Generation

1.4.2 Mapping and Topology Generation for Cluster-Based NoC

1.5 Experimental Results

1.5.1 Baseline Reconfigurable NoC

1.5.2 Performance Evaluation with Cost Constraints

1.5.3 Comparison Cluster-Based NoC

1.6 Conclusion

References

1.1 Introduction

1.1.1 Multicore and Many-Core Era

With the recent scaling of semiconductor technology, coupled with the ever-increasing demand for high-performance computing in embedded, desktop, and server computer systems, the current general-purpose microprocessors have been moving from single-core to multicore and eventually to many-core processor architectures containing tens to hundreds of identical cores [1]. Major manufacturers already ship 10-core [2], 16-core [3, 4], and 48-core [5] chip multiprocessors, while some special-purpose processors have pushed the limit ...