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Logically Determined Design: Clockless System Design with NULL Convention Logic

Logically Determined Design: Clockless System Design with NULL Convention Logic

by Karl Fant
Publisher: Wiley-Interscience
Release Date: January 2005
ISBN: 9780471684787
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Book Description

This seminal book presents a new logically determined design methodology for designing clockless circuit systems. The book presents the foundations, architectures and methodologies to implement such systems. Based on logical relationships, it concentrates on digital circuit system complexity and productivity to allow for more reliable, faster and cheaper products.

  • Transcends shortcomings of Boolean logic.

  • Presents theoritical foundations, architecture and analysis of clockless (asynchronous) circuit design.

  • Contains examples and exercises making it ideal for those studying the area.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Dedication
  5. CONTENTS
  6. PREFACE
    1. ACKNOWLEDGMENTS
  7. CHAPTER 1: Trusting Logic
    1. 1.1 MATHEMATICIANLESS ENLIVENMENT OF LOGIC EXPRESSION
    2. 1.2 EMULATING THE MATHEMATICIAN
    3. 1.3 SUPPLEMENTING THE EXPRESSIVITY OF BOOLEAN LOGIC
    4. 1.4 DEFINING A SUFFICIENTLY EXPRESSIVE LOGIC
    5. 1.5 THE LOGICALLY DETERMINED SYSTEM
    6. 1.6 TRUSTING THE LOGIC: A METHODOLOGY OF LOGICAL CONFIDENCE
    7. 1.7 SUMMARY
    8. 1.8 EXERCISES
  8. CHAPTER 2: A Sufficiently Expressive Logic
    1. 2.1 SEARCHING FOR A NEW LOGIC
    2. 2.2 DERIVING A 3 VALUE LOGIC
    3. 2.3 DERIVING A 2 VALUE LOGIC
    4. 2.4 COMPROMISING LOGICAL COMPLETENESS
    5. 2.5 SUMMARY
  9. CHAPTER 3: The Structure of Logically Determined Systems
    1. 3.1 THE CYCLE
    2. 3.2 BASIC PIPELINE STRUCTURES
    3. 3.3 CONTROL VARIABLES AND WAVEFRONT STEERING
    4. 3.4 THE LOGICALLY DETERMINED SYSTEM
    5. 3.5 INITIALIZATION
    6. 3.6 TESTING
    7. 3.7 SUMMARY
    8. 3.8 EXERCISES
  10. CHAPTER 4: 2NCL Combinational Expression
    1. 4.1 FUNCTION CLASSIFICATION
    2. 4.2 THE LIBRARY OF 2NCL OPERATORS
    3. 4.3 2NCL COMBINATIONAL EXPRESSION
    4. 4.4 EXAMPLE 1: BINARY PLUS TRINARY TO QUATERNARY ADDER
    5. 4.5 EXAMPLE 2: LOGIC UNIT
    6. 4.6 EXAMPLE 3: MINTERM CONSTRUCTION
    7. 4.7 EXAMPLE 4: A BINARY CLIPPER
    8. 4.8 EXAMPLE 5: A CODE DETECTOR
    9. 4.9 COMPLETENESS SUFFICIENCY
    10. 4.10 GREATER COMBINATIONAL COMPOSITION
    11. 4.11 DIRECTLY MAPPING BOOLEAN COMBINATIONAL EXPRESSIONS
    12. 4.12 SUMMARY
    13. 4.13 EXERCISES
  11. CHAPTER 5: Cycle Granularity
    1. 5.1 PARTITIONING COMBINATIONAL EXPRESSIONS
    2. 5.2 PARTITIONING THE DATA PATH
    3. 5.3 TWO-DIMENSIONAL PIPELINING: ORTHOGONAL PIPELINING ACROSS A DATA PATH
    4. 5.4 2D WAVEFRONT BEHAVIOR
    5. 5.5 2D PIPELINED OPERATIONS
    6. 5.6 SUMMARY
    7. 5.7 EXERCISES
  12. CHAPTER 6: Memory Elements
    1. 6.1 THE RING REGISTER
    2. 6.2 COMPLEX FUNCTION REGISTERS
    3. 6.3 THE CONSUME/PRODUCE REGISTER STRUCTURE
    4. 6.4 THE REGISTER FILE
    5. 6.5 DELAY PIPELINE MEMORY
    6. 6.6 DELAY TOWER
    7. 6.7 FIFO TOWER
    8. 6.8 STACK TOWER
    9. 6.9 WRAPPER FOR STANDARD MEMORY MODULES
    10. 6.10 EXERCISES
  13. CHAPTER 7: State Machines
    1. 7.1 BASIC STATE MACHINE STRUCTURE
    2. 7.2 EXERCISES
  14. CHAPTER 8: Busses and Networks
    1. 8.1 THE BUS
    2. 8.2 A FAN-OUT STEERING TREE
    3. 8.3 FAN-IN STEERING TREES DO NOT WORK
    4. 8.4 ARBITRATED STEERING STRUCTURES
    5. 8.5 CONCURRENT CROSSBAR NETWORK
    6. 8.6 EXERCISES
  15. CHAPTER 9: Multi-value Numeric Design
    1. 9.1 NUMERIC REPRESENTATION
    2. 9.2 A QUATERNARY ALU
    3. 9.3 A BINARY ALU
    4. 9.4 COMPARISON
    5. 9.5 SUMMARY
    6. 9.6 EXERCISES
  16. CHAPTER 10: The Shadow Model of Pipeline Behavior
    1. 10.1 PIPELINE STRUCTURE
    2. 10.2 THE PIPELINE SIMULATION MODEL
    3. 10.3 DELAYS AFFECTING THROUGHPUT
    4. 10.4 THE SHADOW MODEL
    5. 10.5 THE VALUE OF THE SHADOW MODEL
    6. 10.6 EXERCISES
  17. CHAPTER 11: Pipeline Buffering
    1. 11.1 ENHANCING THROUGHPUT
    2. 11.2 BUFFERING FOR CONSTANT RATE THROUGHPUT
    3. 11.3 SUMMARY OF BUFFERING
    4. 11.4 EXERCISES
  18. CHAPTER 12: Ring Behavior
    1. 12.1 THE PIPELINE RING
    2. 12.2 WAVEFRONT-LIMITED RING BEHAVIOR
    3. 12.3 THE CYCLE-TO-WAVEFRONT RATIO
    4. 12.4 RING SIGNAL BEHAVIOR
  19. CHAPTER 13: Interacting Pipeline Structures
    1. 13.1 PRELIMINARIES
    2. 13.2 EXAMPLE 1: THE BASICS OF A TWO-PIPELINE STRUCTURE
    3. 13.3 EXAMPLE 2: A WAVEFRONT DELAY STRUCTURE
    4. 13.4 EXAMPLE 3: REDUCING THE PERIOD OF THE SLOWEST CYCLE
    5. 13.5 EXERCISES
  20. CHAPTER 14: Complex Pipeline Structures
    1. 14.1 LINEAR FEEDBACK SHIFT REGISTER EXAMPLE
    2. 14.2 GRAFTING PIPELINES
    3. 14.3 THE LFSR WITH A SLOW CYCLE
    4. 14.4 SUMMARY
    5. 14.5 EXERCISES
  21. Appendix A: Logically Determined Wavefront Flow
    1. A.1 SYNCHRONIZATION
    2. A.2 WAVEFRONTS AND BUBBLES
    3. A.3 WAVEFRONT PROPAGATION
    4. A.4 EXTENDED SIMULATION OF WAVEFRONT FLOW
    5. A.5 WAVEFRONT AND BUBBLE BEHAVIOR IN A SYSTEM
  22. APPENDIX B: Playing with 2NCL
    1. B.1 THE SR FLIP-FLOP IMPLEMENTATIONS
    2. B.2 INITIALIZATION
    3. B.3 AUTO-PRODUCE AND AUTO-CONSUME
  23. APPENDIX C: Pipeline Simulation
  24. REFERENCES
  25. INDEX