Logically Determined Design: Clockless System Design with NULL Convention Logic

INDEX

Acknowledge signal, 34

conditioning, 42–43

Adder

full-adder, 38, 40, 76–77, 82–86

half-adder, 73–76, 86

ripple carry, 86–87, 100–102

Arbiter, 150–159

2D pipelined, 159

2NCL cycle, 151–157

arbitrated fan-in, 151–157

crossbar, 157–159

timing issues, 156

Asynchronous design, 4–5

Bundled data, 28–29

C-element, 4–5

Dual-rail code, 4, 5

matched delay, 29

micropipeline, 28–29

Muller, 4

Binary ALU, 170–172

comparison with quaternary, 172–173

Binary/dual-rail conversion, 128

Boolean logic

and 2NCL, 21–22, 66

and3NCL, 18

and4NCL, 16

clocked, 29

data function, 66–67

enlivening, 1–2

incompleteness, 1–3

mapping to 2NCL, 87–92

NPN classes, 91–92

MUX orientation, 49

supplementing, 2–5

Time interval, 3–4

Bubble, 271

delay, 178–179

flow, 208

path, 176

shadow, 179–183

Buffer(s)(ing), 191

constant rate, 196–203

enhancing throughput, 191–196

structuring, 194–195

inverted bowl, 194

triangular, 106–107

Bus(ses), 141–147

crossbar, 141–147

arbitrated, 157–159

consolidated control, 142

interweaved control, 145–147

serial, 141

C-element, 4–5, 7, 21, 279

circuitmaker, 279

code detector, 133–137

Combinational expression, 59–93

composition, 85–87

minterm synthesis, 73–76

optimization, 73

merging operators, 97–98

output equation, 67–68

minimizing, 78–81

product partitioning, 69, 86

sum-of-products form, ...