CHAPTER 21 / HARDWARE IMPLEMENTATION OF DATA COMPRESSION 417
Several systolic and SIMD arrays for 2D DWTs were proposed in [15-17, 34, 37, 39, 59]. Some
recent works can be found in Refs. [65, 78]. Since there are too many contributions in this area,
we are providing pointers to only some of the important ones.
21.3.3 JPEG Hardware
Several special-purpose VLSI chips implementing the JPEG baseline compression standard have
been built and successfully commercialized. The majority of earlier image products were from
C-Cube, LSI Logic, Zoran, Fujitsu, Intel, and Atmel [87]. Intel's i750 video processor [35, 36]
consisted of two chips, the 82 750-PB pixel processor and the 82 750-DB display processor.
The pixel processor can be programmed to implement the JPEG compression standard. C-Cube
developed two processors, CL560 and CL550 [ 18]. CL550 operates at 35 MHz; data sustenance
was at the rate of 2 MB/s and the compression rate was 30 fields/s. CL560 was installed with
enhanced video applications. The sustenance was 60 MB/s. The chip could handle 601 frames
in real time. LSI Logic announced a chip-set for JPEG compression that consisted of an L64735
DCT processor, an L64745 JPEG coder, and an L74765 color and raster-block converter and
could process still-image data at up to 30 million bytes per second (Mbps). LSI Logic's JPEG
chip-set is described in [53, 54]. In July 1993, LSI Logic announced the L64702 single-chip
JPEG coprocessor designed for graphics and video applications in personal computers, engineer-
ing workstations, and laser printers [ 1 ]. The chip was capable of compressing and decompressing
data at rates up to 8.25 million bytes per second with an operating frequency of 33 MHz. The
architecture of JAGUAR, which implemented the various logic blocks of the entire JPEG com-
pression standard as a linear superpipeline to achieve 100 million bytes per second throughput,
was described in [57]. Zoran offered ZR36040 and ZR36050. ZR36040 works with an external
DCT processor and controller. Data processing could vary from 15 to 21 MB/s and could process
601 CCIR frames in real time. The ZR36050 JPEG chip was designed as a superset of ZR36040,
which had a video encoder and decoder in a single chip. Fujitsu developed MB86357A, which
supported color components with either 8 or 12 bits/pixel with a 20-MHz clock. Atmel targeted
a low-power, low-cost chip suitable for camera or video applications.
In the present scenario, image compression products are seldom developed. Still-image com-
pression is performed by the video compression chip-sets. We found one JPEG image processor
by Oak Technology Inc. The relevant features are discussed below. The product PM-36 is a
fixed-function iCODEC for high-speed color and grayscale image data compression. The data
sustenance is 110 Mbps. This chip can operate at 80 MHz (for raster/block mode) or 110 MHz
(for block mode only). It uses four loadable Q-tables and two loadable Huffman table pairs. The
chip has internal PLL and operates at 3.3 V with 5-V tolerant I/O. The JPEG standards are ISO
IS10918-1/10918-2 for baseline and color images. The chip has internal buffers of 256 bytes on
input and output ports. I/O's can transfer up to 280 Mbps. Figure 21.9 depicts the block diagram
for the PM-36 image processor.
21.4 VIDEO COMPRESSION HARDWARE
In recent years, video communication has become an essential part of a wide range of applications.
Cheap digital storage media and an abundance of digital transmission channels have triggered
a huge growth in video communication. In response to the wide range of applications, various
standards for coding and transmission have been proposed by the ISO and ITU groups. MPEG
standards such as MPEG-1, MPEG-2, and MPEG-4 are commonly used in video communica-
tion, whereas H.261 and H.263 are standards specific to teleconferencing. Video compression

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