Machine Learning Techniques for VLSI Chip Design

5A Detailed Roadmap from Conventional-MOSFET to Nanowire-MOSFET

P. Kiran Kumar^1,2*, B. Balaji1, M. Suman¹, P. Syam Sundar¹, E. Padmaja² and K. Girija Sravani¹

¹ Department of ECE, Koneru Lakshmaiah Educational Foundation (Deemed to be University), Guntur, Andhra Pradesh, India

² Department of ECE, Balaji Institute of Technology, Narasampet, Warangal, India

Abstract

Recently, the need for low-power, high-speed portable devices grew rapidly in the semiconductor industry. The developments in process technology made development of transistors with reduced dimensions, which led to the growth of the number of transistors on ICs. Also, the scaling of transistors along with CMOS technology made continuous upgrading of speed and power consumption of ICs. The scaled down transistor in the sub-100nm regime causes Short Channel Effects (SCE) such as lowering barrier height by drain supply, gate leakage, higher sub-threshold conduction and poly depletion, etc., and the effects of these are reduced by usage of various engineering techniques like metal work function, channel-doping profile and gate oxide. In the sub-45nm regime, the controllability on the channel is enhanced by introducing a new structure Thin-body SOI MOSFET with single and double gate. At 22nm nanometer technology, another new structure Fin-FET is proposed for further enhancement of controllability of gate on the channel. The Fin-FET utilizes double-gate, tri-gate, pi-gate, and omega-gate structures for further improvement ...