Memory Systems

Memory Systems

by Bruce Jacob, David Wang, Spencer Ng
Released July 2010
Publisher(s): Morgan Kaufmann
ISBN: 9780080553849

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Book description

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy.
  • Understand all levels of the system hierarchy -Xcache, DRAM, and disk.
  • Evaluate the system-level effects of all design choices.
  • Model performance and energy consumption for each component in the memory hierarchy.

Table of contents

  1. Cover
  2. Title page
  3. Table of Contents
  4. In Praise of Memory Systems: Cache, DRAM, Disk
  5. Copyright
  6. Dedication
  7. Inside Front Cover
  8. Preface
  9. OVERVIEW: On Memory Systems and Their Design
    1. Ov.1 Memory Systems
    2. Ov.2 Four Anecdotes on Modular Design
    3. Ov.3 Cross-Cutting Issues
    4. Ov.4 An Example Holistic Analysis
    5. Ov.5 What to Expect
  10. Part I: Cache
    1. Chapter 1: An Overview of Cache Principles
      1. 1.1 Caches, ‘Caches,’ and “Caches”
      2. 1.2 Locality Principles
      3. 1.3 What to Cache, Where to Put It, and How to Maintain It
      4. 1.4 Insights and Optimizations
    2. Chapter 2: Logical Organization
      1. 2.1 Logical Organization: A Taxonomy
      2. 2.2 Transparently Addressed Caches
      3. 2.3 Non-Transparently Addressed Caches
      4. 2.4 Virtual Addressing and Protection
      5. 2.5 Distributed and Partitioned Caches
      6. 2.6 Case Studies
    3. Chapter 3: Management of Cache Contents
      1. 3.1 Case Studies: On-Line Heuristics
      2. 3.2 Case Studies: Off-Line Heuristics
      3. 3.3 Case Studies: Combined Approaches
      4. 3.4 Discussions
      5. 3.5 Building a Content-Management Solution
    4. Chapter 4: Management of Cache Consistency
      1. 4.1 Consistency with Backing Store
      2. 4.2 Consistency with Self
      3. 4.3 Consistency with Other Clients
    5. Chapter 5: Implementation Issues
      1. 5.1 Overview
      2. 5.2 SRAM Implementation
      3. 5.3 Advanced SRAM Topics
      4. 5.4 Cache Implementation
    6. Chapter 6: Cache Case Studies
      1. 6.1 Logical Organization
      2. 6.2 Pipeline Interface
      3. 6.3 Case Studies of Detailed Itanium-2 Circuits
  11. Part II: DRAM
    1. Chapter 7: Overview of DRAMs
      1. 7.1 DRAM Basics: Internals, Operation
      2. 7.2 Evolution of the DRAM Architecture
      3. 7.3 Modern-Day DRAM Standards
      4. 7.4 Fully Buffered DIMM: A Compromise of Sorts
      5. 7.5 Issues in DRAM Systems, Briefly
    2. Chapter 8: DRAM Device Organization: Basic Circuits and Architecture
      1. 8.1 DRAM Device Organization
      2. 8.2 DRAM Storage Cells
      3. 8.3 RAM Array Structures
      4. 8.4 Differential Sense Amplifier
      5. 8.5 Decoders and Redundancy
      6. 8.6 DRAM Device Control Logic
      7. 8.7 DRAM Device Configuration
      8. 8.8 Data I/O
      9. 8.9 DRAM Device Packaging
      10. 8.10 DRAM Process Technology and Process Scaling Considerations
    3. Chapter 9: DRAM System Signaling and Timing
      1. 9.1 Signaling System
      2. 9.2 Transmission Lines on PCBs
      3. 9.3 Termination
      4. 9.4 Signaling
      5. 9.5 Timing Synchronization
      6. 9.6 Selected DRAM Signaling and Timing Issues
      7. 9.7 Summary
    4. Chapter 10: DRAM Memory System Organization
      1. 10.1 Conventional Memory System
      2. 10.2 Basic Nomenclature
      3. 10.3 Memory Modules
      4. 10.4 Memory System Topology
      5. 10.5 Summary
    5. Chapter 11: Basic DRAM Memory-Access Protocol
      1. 11.1 Basic DRAM Commands
      2. 11.2 DRAM Command Interactions
      3. 11.3 Additional Constraints
      4. 11.4 Command Timing Summary
      5. 11.5 Summary
    6. Chapter 12: Evolutionary Developments of DRAM Device Architecture
      1. 12.1 DRAM Device Families
      2. 12.2 Historical-Commodity DRAM Devices
      3. 12.3 Modern-Commodity DRAM Devices
      4. 12.4 High Bandwidth Path
      5. 12.5 Low Latency
      6. 12.6 Interesting Alternatives
    7. Chapter 13: DRAM Memory Controller
      1. 13.1 DRAM Controller Architecture
      2. 13.2 Row-Buffer-Management Policy
      3. 13.3 Address Mapping (Translation)
      4. 13.4 Performance Optimization
      5. 13.5 Summary
    8. Chapter 14: The Fully Buffered DIMM Memory System
      1. 14.1 Introduction
      2. 14.2 Architecture
      3. 14.3 Signaling and Timing
      4. 14.4 Access Protocol
      5. 14.5 The Advanced Memory Buffer
      6. 14.6 Reliability, Availability, and Serviceability
      7. 14.7 FB-DIMM Performance Characteristics
      8. 14.8 Perspective
    9. Chapter 15: Memory System Design Analysis
      1. 15.1 Overview
      2. 15.2 Workload Characteristics
      3. 15.3 The RAD Analytical Framework
      4. 15.4 Simulation-Based Analysis
      5. 15.5 A Latency-Oriented Study
      6. 15.6 Concluding Remarks
  12. Part III: Disk
    1. Chapter 16: Overview of Disks
      1. 16.1 History of Disk Drives
      2. 16.2 Principles of Hard Disk Drives
      3. 16.3 Classifications of Disk Drives
      4. 16.4 Disk Performance Overview
      5. 16.5 Future Directions in Disks
    2. Chapter 17: The Physical Layer
      1. 17.1 Magnetic Recording
      2. 17.2 Mechanical and Magnetic Components
      3. 17.3 Electronics
    3. Chapter 18: The Data Layer
      1. 18.1 Disk Blocks and Sectors
      2. 18.2 Tracks and Cylinders
      3. 18.3 Address Mapping
      4. 18.4 Zoned-Bit Recording
      5. 18.5 Servo
      6. 18.6 Sector ID and No-ID Formatting
      7. 18.7 Capacity
      8. 18.8 Data Rate
      9. 18.9 Defect Management
    4. Chapter 19: Performance Issues and Design Trade-Offs
      1. 19.1 Anatomy of an I/O
      2. 19.2 Some Basic Principles
      3. 19.3 BPI vs. TPI
      4. 19.4 Effect of Drive Capacity
      5. 19.5 Concentric Tracks vs. Spiral Track
      6. 19.6 Average Seek
    5. Chapter 20: Drive Interface
      1. 20.1 Overview of Interfaces
      2. 20.2 ATA
      3. 20.3 Serial ATA
      4. 20.4 SCSI
      5. 20.5 Serial SCSI
      6. 20.6 Fibre Channel
      7. 20.7 Cost, Performance, and Reliability
    6. Chapter 21: Operational Performance Improvement
      1. 21.1 Latency Reduction Techniques
      2. 21.2 Command Queueing and Scheduling
      3. 21.3 Reorganizing Data on the Disk
      4. 21.4 Handling Writes
      5. 21.5 Data Compression
    7. Chapter 22: The Cache Layer
      1. 22.1 Disk Cache
      2. 22.2 Cache Organizations
      3. 22.3 Caching Algorithms
    8. Chapter 23: Performance Testing
      1. 23.1 Test and Measurement
      2. 23.2 Basic Tests
      3. 23.3 Benchmark Tests
      4. 23.4 Drive Parameters Tests
    9. Chapter 24: Storage Subsystems
      1. 24.1 Data Striping
      2. 24.2 Data Mirroring
      3. 24.3 RAID
      4. 24.4 SAN
      5. 24.5 NAS
      6. 24.6 iSCSI
    10. Chapter 25: Advanced Topics
      1. 25.1 Perpendicular Recording
      2. 25.2 Patterned Media
      3. 25.3 Thermally Assisted Recording
      4. 25.4 Dual Stage Actuator
      5. 25.5 Adaptive Formatting
      6. 25.6 Hybrid Disk Drive
      7. 25.7 Object-Based Storage
    11. Chapter 26: Case Study
      1. 26.1 The Mechanical Components
      2. 26.2 Electronics
      3. 26.3 Data Layout
      4. 26.4 Interface
      5. 26.5 Cache
      6. 26.6 Performance Testing
  13. Part IV: Cross-Cutting Issues
    1. Chapter 27: The Case for Holistic Design
      1. 27.1 Anecdotes, Revisited
      2. 27.2 Perspective
    2. Chapter 28: Analysis of Cost and Performance
      1. 28.1 Combining Cost and Performance
      2. 28.2 Pareto Optimality
      3. 28.3 Taking Sampled Averages Correctly
      4. 28.4 Metrics for Computer Performance
      5. 28.5 Analytical Modeling and the Miss-Rate Function
    3. Chapter 29: Power and Leakage
      1. 29.1 Sources of Leakage in CMOS Devices
      2. 29.2 A Closer Look at Subthreshold Leakage
      3. 29.3 νCACTI and Energy/Power Breakdown of Pipelined Nanometer Caches
    4. Chapter 30: Memory Errors and Error Correction
      1. 30.1 Types and Causes of Failures
      2. 30.2 Soft Error Rates and Trends
      3. 30.3 Error Detection and Correction
      4. 30.4 Reliability of Non-DRAM Systems
      5. 30.5 Space Shuttle Memory System
    5. Chapter 31: Virtual Memory
      1. 31.1 A Virtual Memory Primer
      2. 31.2 Implementing Virtual Memory
  14. References
  15. Index

Product information

  • Title: Memory Systems
  • Author(s): Bruce Jacob, David Wang, Spencer Ng
  • Release date: July 2010
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080553849