Microprocessor 2

Exercises

Below are some exercises that follow on from the notions covered in this work. The number scheme reflects the chapter with which they are associated.

Chapter 1. Exercises

E1.1. Create a logic diagram of a validation system of binary data (format n = 2 bits) using three-state data encoding (cf. § 1.4).

Answer. The system has to send an acknowledgment signal when the data is valid, with input values (0, 0) and (1, 1) respectively marking an invalid piece of data, and a non-utilized state. This data can be the result of an operation, in which case the acknowledgment signal is a computation termination signal. Figure E1.53 shows a logic diagram based on a Muller C-element (Muller and Bartky 1959; Muller 1963), the function of which was explained in § 3.4.2 in Darche (2002).

Figure E1.53. Dual-rail code validation system (n = 2 bits)

E1.2. What is bus arbitration?

Answer. Arbitration is the mechanism that determines who will be in possession of the bus when there are several simultaneous access requests.

E1.3. Provide two arbiter logic diagrams.

Answer. The two base models are the ripple arbiter and the look-ahead arbiter, whose logic diagrams are shown in Figure E1.54(a) and E1.54(b) respectively. The terms used are similar to those for the natural binary adders (NB(C) for Natural Binary (Code), cf. § 2.6.1 in Darche (2002)) in relation to the propagation of internal ...