Microprocessor 2

2Transactions and Special Cycles

This chapter focuses on transactions. These are important as they provide a solution to the bottleneck problem. In this context, we shall cover the following modes of transfer: pipelined, split and Out-of-Order (OoO, an extension of the split mode). Moreover, in addition to the classical cycles of read and write, this chapter also covers cycles that are termed “special”, such as broadcasting and block transfers.

2.1. Transaction

A transaction is made up of a sequence of messages. A message is the base unit of any information. It comprises an address, data and an access type. The three phases of a bus cycle are access request (usually in a multi-master environment), addressing and data transfer. There is also sometimes a termination phase. The request itself is split into a request, an arbitration and a grant of possession of the bus.

2.1.1. Transaction pipeline

All of the (sub)phases of a transaction that are normally carried out sequentially can also be executed in parallel if they are placed into the different functional stages of a pipeline. This is called a pipelined bus, with a pipelined transaction. This approach involves functionally splitting the transaction into sub-steps in order to execute them in parallel in the same number of stages. This is used in Synchronous Static and Dynamic Random Access Memory (SSRAM and SDRAM, cf. § 4.5.1 and 6.1 in Darche (2012)). Figure 2.1 shows how a write operation can be split into phases. The request ...