Microprocessor 2

4Bus Classifications

The primary purpose of this chapter is to present the different topologies of bus-based architectures. It also covers buses currently used in the computer industry.

4.1. Multibus architecture

Initially, all the entities shared the same bus, called a “shared bus”, or “linear bus” (DEC PDP-11 vocabulary), when there was only one bus connecting all of the subunits inside a computer (CPU for Central Processing Unit), memory, devices and the display terminal). All sorts of information and signals would pass through this bus, at variable bitrates. Table 4.1 gives a summary of the exchanges between masters and slaves.

Table 4.1. Exchange types between the master and the slave

Transfer from/to	CPU	Memory	I/O
CPU	Interrupt request message	Medium bitrate information (data)	I/O control/command Low bitrate information
Memory	Medium bitrate information (instruction and data)	High bitrate information (DMA transfer/burst)	High bitrate information (DMA transfer/burst)
Input/Output (I/O)	Status of the I/O Low bitrate information interrupt request	High bitrate information (DMA transfer/burst)	High bitrate information (DMA transfer/burst)

Despite mechanisms such as the interrupt request or Direct Memory Access (DMA, cf. § 2.2.2), and with the ever-rising speeds of the central units, isolation of the slower entities – that is, the I/O and the memories – has become a necessity. The natural consequence of this process has been the splitting of buses into several levels, ...