Microprocessor 4

1Coding and Addressing Modes

This chapter focuses on two important characteristics of Instruction Set Architecture (ISA) (cf. § V1-3.5), which are instruction encoding and addressing modes.

1.1. Encoding and formatting an instruction

The instruction¹ is represented in a computer using a binary word in the format i bits, a multiple of the format n of the data and, in general, a multiple of the byte. We use the expression machine code to mean all those binary words representing the instruction to be executed. Instruction encoding depends on the architecture of the target processor. It is formed at least of an instruction code and, potentially, of one or more operands as Figure 1.1 illustrates.

Figure 1.1. Breakdown of an instruction

This instruction can be broken down into fields². The instruction code, also called operation code (abridged to opcode), in format c, has one or more fields. The essential one is the function code. It defines the operation to be executed. Its format of f bits defines the maximum number of instructions F (= 2^f) in the instruction set³. Other fields can be added to this such as, for example, one that specifies the addressing mode (the addressing mode field) of the operands to the format as Figure 1.2 illustrates (VAX⁴ approach from the Digital Equipment Corporation (DEC)). The processor therefore has 2^a addressing modes. Besides simplifying the encoding, ...