Microprocessor Theory and Applications with 68000/68020 and Pentium

9

68020 HARDWARE AND INTERFACING

In this chapter we describe the fundamental concepts associated with hardware aspects of the Motorola 68020 microprocessor. Significant modifications have been made to the 68020 bus structure beyond those of the 68000. One of these enhancements is dynamic bus sizing. Hence, this feature along with 68020 system design concepts are included. Topics covered in this chapter include 68020 pins and signals, dynamic bus sizing, and system design concepts. Finally, design concepts associated with a 68020-based voltmeter and a 68020-based microcomputer interface to a hexadecimal keyboard and a seven-segment display are covered. These topics are described in a simplified manner. Note that a background in the 68000 software and hardware described in Chapters 6 and 7 is required to understand the topics contained in this chapter.

9.1 Introduction

In this section we describe hardware aspects of the 68020. Topics include 68020 pins and signals, aligned and misaligned transfers, dynamic bus sizing, and timing diagrams. Numerous changes have been made to the 68020 bus structure. Note that the 68020 does not support 6800-type I/O devices. As mentioned in Chapter 7, the 68000 supports both 6800-type I/O devices such as 6821 and 16-bit devices such as 68230. Also, the 68020 can complete read or write bus cycles in three clock cycles without wait states. This is due to enhancements made in the 68020 bus control logic. The 68000, on the other hand, requires four cycles ...