Chapters 1 and 2 have familiarized us with the phase-locked loop (PLL), the fundamental building block of all modern frequency synthesizers. We now understand the various types and orders of loops, the performance of the loop, and the evaluation of the loop.

This chapter deals with special loops that are basically one-loop synthesizers. These systems can be combined, as we will see later, in multiloop synthesizers, or some of them can be used as stand-alone systems.

The resolution or step size of the synthesizer, as we have learned, is equal to the reference frequency. There is a conflict between speed and step size, and this chapter deals with ways of minimizing this conflict. First, we will take a look at a system generating frequencies digitally with the help of logic circuitry and/or a digital computer. As today's technology provides us with fast microprocessors, these systems, using microprocessors and lookup tables, are capable of ultrafine-resolution synthesizers.

Then we take a look at multiloop sampler loops, where the various samplers are being used to speed up the response of the very narrow loops commonly required in high-resolution systems. Loops with sequential phase shifters allow increased resolution at the expense of absolute accuracy.

Then we will see how a delay line can be used to improve noise performance. This is almost the reverse technique of what we saw in Chapter 2, where the delay line was used to measure the phase noise.

Finally, we acquaint ...

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