Modeling and Optimization of Parallel and Distributed Embedded Systems

Chapter 5A Queueing Theoretic Approach for Performance Evaluation of Low-Power Multicore-Based Parallel Embedded Systems^*

With Moore's law supplying billions of transistors on-chip, embedded systems are undergoing a paradigm shift from single core to multicore to exploit this high transistor density for high performance. This paradigm shift has led to the emergence of diverse multicore embedded systems in a plethora of application domains (e.g., high-performance computing, dependable computing, mobile computing). Many modern embedded systems integrate multiple cores (whether homogeneous or heterogeneous) on-chip to satisfy computing demand while maintaining design constraints (e.g., energy, power, performance). For example, a 3G mobile handset's signal processing requires 35–40 giga operations per second (GOPS). Considering the limited energy of a mobile handset battery, these performance levels must be met with a power dissipation budget of approximately 1 W, which translates to a performance efficiency of 25 mW/GOPS or 25 pJ/operation for the 3G receiver [143]. These demanding and competing power-performance requirements make modern embedded system design challenging.

Increasing customer expectations/demands for embedded system functionality has led to an exponential increase in design complexity. While industry focuses on increasing the number of on-chip processor cores to meet customer performance demands, embedded system designers face the new challenge of optimal layout ...