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Modeling and Optimization of Parallel and Distributed Embedded Systems by Sanjay Ranka, Ann Gordon-Ross, Arslan Munir

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Chapter 11Parallelized Benchmark-Driven Performance Evaluation of Symmetric Multiprocessors and Tiled Multicore Architectures for Parallel Embedded Systems*

As chip transistor counts increase, embedded system design has shifted from single-core to multicore and manycore architectures. A primary reason for this architecture reformation is that performance speedups are becoming more difficult to achieve by simply increasing the clock frequency of traditional single-core architectures because of limitations in power dissipation. This single-core to multicore paradigm shift in embedded systems has introduced parallel computing to the embedded domain, which was previously predominantly used in supercomputing only. Furthermore, with respect to the computing industry, this paradigm has led to the proliferation of diverse multicore architectures, which necessitates comparison and evaluation of these disparate architectures for different embedded domains (e.g., distributed, real time, reliability constrained).

Contemporary multicore architectures are not designed to deliver high performance for all embedded domains, but are instead designed to provide high performance for a subset of these domains. The precise evaluation of multicore architectures for a particular embedded domain requires executing complete applications prevalent in that domain. Despite the diversity of embedded domains, the critical application for many embedded domains (especially distributed embedded domains of which ...

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