Modeling Embedded Systems and SoC's

Modeling Embedded Systems and SoC's

by Axel Jantsch
Released June 2003
Publisher(s): Morgan Kaufmann
ISBN: 9780080511825

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Book description

Over the last decade, advances in the semiconductor fabrication process have led to the realization of true system-on-a-chip devices. But the theories, methods and tools for designing, integrating and verifying these complex systems have not kept pace with our ability to build them. System level design is a critical component in the search for methods to develop designs more productively. However, there are a number of challenges that must be overcome in order to implement system level modeling. This book directly addresses that need by developing organizing principles for understanding, assessing, and comparing the different models of computation necessary for system level modeling. Dr. Axel Jantsch identifies the representation of time as the essential feature for distinguishing these models. After developing this conceptual framework, he presents a single formalism for representing very different models, allowing them to be easily compared. As a result, designers, students, and researchers are able to identify the role and the features of the "right" model of computation for the task at hand.

*Offers a unique and significant contribution to the emerging field of models of computation *Presents a systematic way of understanding and applying different Models of Computation to embedded systems and SoC design*Offers insights and illustrative examples for practioners, researchers and students of complex electronic systems design.

Table of contents

  1. Copyright
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. Foreword
  4. Preface
    1. How to Read This book: A Roadmap
    2. Who Should Read This Book
    3. Acknowledgments
  5. Notation
  6. One. Introduction
    1. 1.1. Motivation
    2. 1.2. Heterogeneous Models
    3. 1.3. Separation of Computation and Communication
    4. 1.4. Systems and Models
      1. 1.4.1. System Properties
        1. State-less and State-full Systems
        2. Time-Varying and Time-Invariant Systems
        3. System State
        4. Linear and Nonlinear Systems
        5. Deterministic, Stochastic, and Nondeterministic Systems
        6. Events
        7. Time-Driven and Event-Driven Systems
      2. 1.4.2. System Classification Summary
    5. 1.5. The Rugby Metamodel
      1. 1.5.1. Domain, Hierarchy, and Abstraction
        1. Hierarchy
        2. Abstraction
        3. Domain
    6. 1.6. Domains
      1. 1.6.1. Computation
        1. Transistor and Logic Gate Level
        2. The Instruction Set Level
        3. The algorithmic level
        4. System Functions and Relations
      2. 1.6.2. Data
      3. 1.6.3. Time
      4. 1.6.4. Communication
    7. 1.7. Notation
    8. 1.8. Design Methods and Methodology
      1. 1.8.1. Design phases
      2. 1.8.2. Design and Synthesis
      3. 1.8.3. Analysis
    9. 1.9. Case Study: A Design Project
      1. 1.9.1. Requirements Definitions
      2. 1.9.2. System Model
      3. 1.9.3. Software: The C Model
      4. 1.9.4. Software: The Assembler Model
      5. 1.9.5. Hardware: The VHDL Model
      6. 1.9.6. Hardware: Synthesized Netlist
      7. 1.9.7. Discussion
    10. 1.10. Further Reading
    11. 1.11. Exercises
  7. Two. Behavior and Concurrency
    1. 2.1. Models for the Description of Behavior
    2. 2.2. Finite State Machines
      1. 2.2.1. Basic Definition
      2. 2.2.2. Nondeterministic Finite State Machines
      3. 2.2.3. Finite State Machines with ∊-Moves
      4. 2.2.4. State Aggregation
      5. 2.2.5. Regular Sets and Expressions
      6. 2.2.6. Finite State Machines with Output
      7. 2.2.7. Finite State Machine Extensions
    3. 2.3. Petri Nets
      1. 2.3.1. Inputs and Outputs
      2. 2.3.2. Petri Nets and Finite State Machines
      3. 2.3.3. Modeling Templates
        1. Sequence and Concurrency
        2. Fork and Join
        3. Conflict
        4. Mutual Exclusion
        5. Producer/Consumer Relationship
        6. Dining Philosophers
      4. 2.3.4. Analysis Methods for Petri Nets
        1. Boundedness
        2. Conservation
        3. Liveness
        4. Reachability and Coverability
        5. Persistence
      5. 2.3.5. The Coverability Tree
        1. Safeness and Boundedness
        2. Conservation
        3. Coverability
        4. Limitations
    4. 2.4. Extended and Restricted Petri Nets
    5. 2.5. Further Reading
    6. 2.6. Exercises
  8. Three. The Untimed Model of Computation
    1. 3.1. The MoC Framework
    2. 3.2. Processes and Signals
    3. 3.3. Signal Partitioning
    4. 3.4. Process Constructors
    5. 3.5. Process Properties
      1. 3.5.1. Monotonicity
      2. 3.5.2. Continuity
      3. 3.5.3. Sequential Processes
    6. 3.6. Composition Operators
      1. 3.6.1. Parallel Composition
      2. 3.6.2. Sequential Composition
      3. 3.6.3. Feedback Operator
    7. 3.7. Definition of the Untimed MoC
    8. 3.8. Characteristic Functions
    9. 3.9. Process Signatures
    10. 3.10. Process Up-rating
      1. 3.10.1. Map-Based Processes
      2. 3.10.2. Scan-Based Processes
      3. 3.10.3. Mealy-Based Processes
      4. 3.10.4. Processes with Multiple Inputs
      5. 3.10.5. Up-rating and Process Composition
    11. 3.11. Process Down-rating
    12. 3.12. Process Merge
      1. 3.12.1. Perfect Match
        1. Map-Based Processes
        2. Scan-Based Processes
        3. Mealy-Based Processes
      2. 3.12.2. Rational Match
    13. 3.13. Rugby Coordinates
    14. 3.14. The Untimed Computational Model and Petri Nets
    15. 3.15. Synchronous Dataflow
      1. 3.15.1. Single-Processor Schedule
        1. The Rank Test
        2. Initial Buffer Conditions
        3. Minimum Buffer Scheduling
      2. 3.15.2. Multiprocessor Schedule
        1. Compute a PASS
        2. Determine the Unroll Factor J
        3. Construct the Precedence Graph
        4. Compute a PAPS
    16. 3.16. Variants of the Untimed MoC
    17. 3.17. Further Reading
    18. 3.18. Exercises
  9. Four. The Synchronous Model of Computation
    1. 4.1. Perfect Synchrony
    2. 4.2. Process Constructors
    3. 4.3. Feedback Loops
    4. 4.4. Perfectly Synchronous MoC
    5. 4.5. Process Merge
    6. 4.6. Clocked Synchronous Models
    7. 4.7. Extended Characteristic Function
    8. 4.8. Example: Traffic Light Controller
    9. 4.9. Rugby Coordinates
    10. 4.10. Validation
      1. 4.10.1. A U-Turn Section Controller
      2. 4.10.2. Monitors
      3. 4.10.3. Validation Strategies
    11. 4.11. Further Reading
    12. 4.12. Exercises
  10. Five. The Timed Model of Computation
    1. 5.1. Introduction
    2. 5.2. Process Constructors
      1. 5.2.1. Timed MoC Variants
        1. Timer-Based Process Invocation (mealyPT)
        2. Event-Count-Based process invocation (mealyST)
        3. Event Count with Time-out (mealyTT)
      2. 5.2.2. Representation and Distribution of Global Time
        1. Local Timer
        2. Time Tags
        3. Absent Events
        4. Discussion
    3. 5.3. Discrete Event Models Based on δ-Delay
      1. 5.3.1. The Two-Level Time Structure
      2. 5.3.2. The Event-Driven Simulation Cycle
    4. 5.4. Rugby Coordinates
    5. 5.5. Applications
    6. 5.6. Further Reading
    7. 5.7. Exercises
  11. Six. MoC Interfaces
    1. 6.1. Interfaces between Domains of the Same MoC
    2. 6.2. Interfaces between Different Computational Models
      1. 6.2.1. Strip-Based Interface Constructors
      2. 6.2.2. Insert-Based Interface Constructors
    3. 6.3. Integrated Model of Computation
    4. 6.4. Asynchronous Interfaces
    5. 6.5. Process Migration
    6. 6.6. Applications
    7. 6.7. Further Reading
    8. 6.8. Exercises
  12. Seven. Tightly Coupled Process Networks
    1. 7.1. Nonblocking Read
    2. 7.2. Blocking Read and Blocking Write
    3. 7.3. Oversynchronization
    4. 7.4. Rugby Coordinates
    5. 7.5. Further Reading
    6. 7.6. Exercises
  13. Eight. Nondeterminism and Probability
    1. 8.1. The Descriptive Purpose
      1. 8.1.1. Determinate Models
      2. 8.1.2. Nondeterminate Models
        1. Dataflow Networks
        2. Process Algebras
    2. 8.2. The Constraining Purpose
    3. 8.3. The σ Process
    4. 8.4. Synthesis and Formal Verification
    5. 8.5. Process Constructors
      1. 8.5.1. select-Based Constructors
      2. 8.5.2. Consolidation-Based Constructors
    6. 8.6. Usage of Stochastic Skeletons
      1. 8.6.1. The Descriptive Purpose
      2. 8.6.2. The Constraining Purpose
    7. 8.7. Further Reading
    8. 8.8. Exercises
  14. Nine. Applications
    1. 9.1. Performance Analysis
      1. 9.1.1. Untimed Analysis
        1. Analysis
        2. Simulation
      2. 9.1.2. Timed Analysis
    2. 9.2. Functional Specification
      1. 9.2.1. Example: Number Sorter
      2. 9.2.2. Example: Packet Multiplexer
      3. 9.2.3. Role of a Functional Specification
    3. 9.3. Design and Synthesis
      1. 9.3.1. Design Problems and Decisions
        1. Components and Architecture
        2. Tasks and Code Generation
        3. Constraints and Objectives
      2. 9.3.2. Consequences for Modeling
      3. 9.3.3. Review of MoCs
        1. Timed Model
        2. Synchronous Model
        3. Untimed Model
    4. 9.4. Further Reading
    5. 9.5. Exercises
  15. Ten. Concluding Remarks
  16. Bibliography

Product information

  • Title: Modeling Embedded Systems and SoC's
  • Author(s): Axel Jantsch
  • Release date: June 2003
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080511825