Multicore DSP

2The TMS320C66x architecture overview

CHAPTER MENU

1. 2.1 Overview
2. 2.2 The CPU
   1. 2.2.1 Cross paths
      1. 2.2.1.1 Data cross paths
      2. 2.2.1.2 Address cross paths
   2. 2.2.2 Register file A and file B
      1. 2.2.2.1 Operands
   3. 2.2.3 Functional units
      1. 2.2.3.1 Condition registers
      2. 2.2.3.2 .L units
      3. 2.2.3.3 .M units
      4. 2.2.3.4 .S units
      5. 2.2.3.5 .D units
3. 2.3 Single instruction, multiple data (SIMD) instructions
   1. 2.3.1 Control registers
4. 2.4 The KeyStone memory
   1. 2.4.1 Using the internal memory
   2. 2.4.2 Memory protection and extension
   3. 2.4.3 Memory throughput
5. 2.5 Peripherals
   1. 2.5.1 Navigator
   2. 2.5.2 Enhanced Direct Memory Access (EDMA) Controller
   3. 2.5.3 Universal Asynchronous Receiver/Transmitter (UART)
   4. 2.5.4 General purpose input–output (GPIO)
   5. 2.5.5 Internal timers
6. 2.6 Conclusion
7. References

2.1 Overview

Building on a previous success with the first digital signal processor (DSP) generation based on the Texas Instruments (TI) VelociTI^TM architecture TMS320C6000, which used an enhancement of the VLIW (very long instruction word) architecture, TI has now pushed the frontiers a bit further by embracing the multicore system‐on‐chip (SoC) technology and adding many features, such as: enhanced architecture, more configurable coprocessors, tiered memory architecture, high speed, a low‐latency point‐to‐point communication interface known as the HyperLink, a TeraNet switch fabric which provides fast interconnection between the DSP CorePacs, the ARM CorePacs when available, memory, peripherals and a Multicore Navigator that ...