Multicore DSP

8Enhanced Direct Memory Access (EDMA3) controller

CHAPTER MENU

1. 8.1 Introduction
2. 8.2 Type of DMAs available
3. 8.3 EDMA controllers architecture
   1. 8.3.1 The EDMA3 Channel Controller (EDMA3CC)
   2. 8.3.2 The EDMA3 transfer controller (EDMA3TC)
   3. 8.3.3 EDMA prioritisation
      1. 8.3.3.1 Trigger source priority
      2. 8.3.3.2 Channel priority
      3. 8.3.3.3 Dequeue priority
      4. 8.3.3.4 System (transfer controller) priority
4. 8.4 Parameter RAM (PaRAM)
   1. 8.4.1 Channel options parameter (OPT)
5. 8.5 Transfer synchronisation dimensions
   1. 8.5.1 A – Synchronisation
   2. 8.5.2 AB – Synchronisation
6. 8.6 Simple EDMA transfer
7. 8.7 Chaining EDMA transfers
8. 8.8 Linked EDMAs
9. 8.9 Laboratory experiments
   1. 8.9.1 Laboratory 1: Simple EDMA transfer
   2. 8.9.2 Laboratory 2: EDMA chaining transfer
   3. 8.9.3 Laboratory 3: EDMA link transfer
10. 8.10 Conclusion
11. References

8.1 Introduction

There are two methods for transferring data from one part of the memory or peripheral to another. These methods are:

1. CPU transfer
2. Direct Memory Access (DMA) transfer.

Using the CPU to transfer data is very simple (using load and store instructions), but it is time‐consuming as the CPU will not be free to perform other tasks while transferring data.

If a DMA is used, then the CPU only needs to configure the DMA. Whilst the transfer is taking place, the CPU is then free to perform other operations. The KeyStone devices have an Enhanced Direct Memory Access version 3 (EDMA3) controller that is very flexible, as demonstrated later in this chapter. The EDMA has the following ...