Multicore DSP

9Inter‐Processor Communication (IPC)

CHAPTER MENU

1. 9.1 Introduction
2. 9.2 Texas Instruments IPC
3. 9.3 Notify module
   1. 9.3.1 Laboratory experiment
4. 9.4 MessageQ
   1. 9.4.1 MessageQ protocol
   2. 9.4.2 Message priority
   3. 9.4.3 Thread synchronisation
5. 9.5 ListMP module
6. 9.6 GateMP module
   1. 9.6.1 Initialising a GateMP parameter structure
      1. 9.6.1.1 Types of gate protection
   2. 9.6.2 Creating a GateMP instance
   3. 9.6.3 Entering a GateMP
   4. 9.6.4 Leaving a gate
   5. 9.6.5 The list of functions that can be used by GateMP
7. 9.7 Multi‐processor Memory Allocation: HeapBufMP, HeapMemMP and HeapMultiBufMP
   1. 9.7.1 HeapBuf_Params
   2. 9.7.2 HeapMem_Params
   3. 9.7.3 HeapMultiBuf_Params
   4. 9.7.4 Configuration example for HeapMultiBuf
8. 9.8 Transport mechanisms for the IPC
9. 9.9 Laboratory experiments with KeyStone I
   1. 9.9.1 Laboratory 1: Using MessageQ with multiple cores
      1. 9.9.1.1 Overview
   2. 9.9.2 Laboratory 2: Using ListMP, ShareRegion and GateMP
10. 9.10 Laboratory experiments with KeyStone II
    1. 9.10.1 Laboratory experiment 1: Transferring a block of data
       1. 9.10.1.1 Set the connection between the host (PC) and the KeyStone
       2. 9.10.1.2 Explore the ARM code
       3. 9.10.1.3 Explore the DSP code
       4. 9.10.1.4 Compile and run the program
    2. 9.10.2 Laboratory experiment 2: Transferring a pointer
       1. 9.10.2.1 Explore the ARM code
       2. 9.10.2.2 Explore the DSP code
       3. 9.10.2.3 Compile and run the program
11. 9.11 Conclusion
12. References

9.1 Introduction

Having a processor with multicores has many advantages, as is seen in previous chapters. However, not having the cores communicating very efficiently ...