Multiprocessor Systems-on-Chips

4.3. Pipelining Techniques

Pipelines improve instruction throughput as long as the flow of instructions is not disrupted. In this section, we review the various types of pipeline hazards that may cause instructions to stall, as well as techniques that are used to minimize these stalls. This overview provides a context for discussing existing embedded processors (e.g., ARM, MIPS, PowerPC) in Section 4.4, as well as future embedded processors.

4.3.1. Bypasses

A data hazard exists when an instruction depends on data produced by a previous instruction, and the previous instruction has not yet completed (result has not been written to the register file). As shown in Figure 4-5, instruction 2 depends on a value produced by instruction 1, and so it ...