7.1. Introduction

On-chip communication is increasingly being regarded as one of the major hurdles for complex system-on-chip (SoC) designs [274]. As technology scales into the nanometer era, chip-level wiring presents numerous challenges, including large signal propagation delays, high-power dissipation, and increased susceptibility to errors [275,276]. On the other hand, at the system-level, the integration of an increasing number and variety of complex components is resulting in rapid growth in the volume and diversity of on-chip communication traffic, imposing stringent requirements on the underlying on-chip communication resources. As a result, on-chip communication has started to play a significant role in determining several system-wide ...

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