8.5. The Architectural Platform
In this project we mapped the Hiperlan/2 model onto a real reconfigurable and heterogeneous platform for low-power transceivers used in wireless applications.
It is specialized for an OFDM-based physical layer but also supports the implementation of high-level protocol tasks on an embedded processor.
Several cores are connected through a flexible communication resource, a crossbar bus called XBar in Figure 8-8. Some of the cores, i.e., FFT and FIR, implement computation-intensive functions as highly optimized IP with limited range of programmability. Other cores are very flexible. An embedded low-power FPGA [357] provides bit-level programmability, and a RISC microcontroller provides resources for dataflow management ...
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