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Bottom-Up Approaches for CMOS Scaling in the Nanoscale Era
Mrunal A. Khaderbad, V. Ramgopal Rao
4.1 Self-Assembled Monolayers
4.3 Issues Related to CMOS Scaling
4.4 Porphyrin SAMs as Copper Diffusion Barriers
4.4.1 Copper/Low-k Technologies in ULSI Metallization
4.4.2 Cu Diffusion Barriers in ULSI Metallezation
4.4.3 Porphyrin SAMs as Cu Diffusion Barriers in ULSI Metallization
126.96.36.199 Bias–Temperature–Stress Analysis
188.8.131.52 Secondary Ion Mass Spectrometry
4.5 Porphyrin SAMs For Metal Gate Work Function Tuning
4.5.1 Potential Gate Electrodes for Work Function Engineering
4.5.2 Porphyrin SAMs for Work Function Engineering
184.108.40.206 HFCV Analysis
4.6 Unipolar Graphene Field Effect Transistors ...
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