CONTENTS
18.1 Introduction
18.2 Background
18.2.1 QCA Cell
18.2.2 Logic Gates in QCA
18.2.3 Clock Zones
18.2.4 Coplanar Wire Crossings
18.3 Restoring Binary Divider
18.3.1 Conventional Restoring Binary Divider Architecture
18.3.2 Restoring Array Divider for QCA
18.4 Implementation Details
18.4.1 Design Guidelines for Robust QCA Circuits
18.4.2 Implementation of the Restoring Divider
18.4.2.1 Basic Elements for Restoring Array Divider
18.4.2.2 Controlled Full Subtractor Cell
18.4.2.3 Comparison of Coplanar and Multilayer Wire Crossings
18.4.2.4 Timing Analysis
18.5 Simulation Results
18.5.1 Restoring Divider Results
18.5.2 Comparison ...
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