Nanoelectronics

241

6

Nano-MOSFET and Nano-CMOS

The advances in ULSI technology are heavily based on downscaling of the

minimum feature size of a metal-oxide-semiconductor eld-effect-transistor

(MOSFET) [1,2]. NMOS (n-type MOSFET) and PMOS (p-type MOSFET) pair

comprises a CMOS inverter circuit. The recent evolution of nanotechnology

may provide challenges and opportunities for novel devices, such as single-

electron devices, carbon nanotubes, Si nanowires, and new materials. The

utilization of quantum effects and ballistic transport characteristics may also

provide novel functions for silicon-based devices. Among various candidate

materials for nanometer-scale devices, silicon nanodevices are particularly

promising because of the existing silicon process infrastructure in semicon-

ductor industries, the compatibility to CMOS circuits, and a nearly perfect

interface between the natural oxide and silicon. Nanoscale MOSFETs are par-

ticularly of great interest to discover fundamental physics as well as applica-

tions to the technology for product development. MOSFETs are grown on

(100)-substrate for a better silicon dioxide (SiO

2

) interface.

6.1 Primer

The mobility and saturation velocity are the two important parameters that

control the charge transport in a conducting MOSFET channel [3]. The mobil-

ity is degraded by both the gate electric eld and the channel electric eld;

the former is due to quantum connement and the latter is due to streaming

of velocity vectors in the intense driving electric eld. The saturation veloc-

ity in the channel is ballistic, which is limited to the thermal velocity for

nondegenerate carriers and to the Fermi velocity for degenerate carriers in

the inversion regime. The drain-end carrier velocity is always smaller than

the ultimate saturation velocity due to the presence of the nite electric eld

at the drain. The popular channel pinchoff assumption is reexamined for

either a long or SC. Channel conduction beyond quasi-pinchoff arises from

an increase in the drain velocity as a result of the enhanced electric eld as

the drain voltage is increased, giving an alternative description of the chan-

nel-length modulation. The current–voltage characteristics of a nanoscale

MOSFET in the inversion regime is the subject of this chapter.

The MOSFET of Figure 6.1 is a vehicle for the design of an integrated

circuit both for digital and analog applications. It has a long history of

242 Nanoelectronics

channel length being scaled down that is now in the deca–nanometer

regime. The fundamental processes that control the performance of the

MOSFET channel continue to elude physicists and engineers alike. Figure 6.1

demonstrates that in a nanoscale channel, where oxide thickness is a few nm,

the separation z

QM

of electrons from the interface due to the quantum-con-

nement effect cannot be ignored. The gate electric eld E

t

does not heat elec-

trons as it is not an accelerating eld; rather, it is a conning electric eld that

makes an electron a quantum entity described by the wave character with

discrete (digitized) energy levels. The wavefunction vanishes at the Si/SiO

2

interface and peaks at a distance approximately z

QM

away from the interface.

This alters the gate capacitance and hence the carrier density in the channel.

MOSFET channel, like any other conducting channel, is created by the

application of gate voltage V

GS

that is above the threshold voltage for the

channel to grow as the overdrive voltage V

GT

= V

GS

− V

T

is increased. Care

should be taken not to confuse V

T

with thermal voltage V

t

that also appears

in the subthreshold swing. This is the principle of MOS-capacitor (MOS-C)

discussed in the next section. The charge in the channel ows due to the

drain voltage applied between the gate and the source. Normally, the source

is put at the ground potential (V

S

= 0). V

T

is adjustable by applied voltage to

the body of the MOSFET with respect to the source. For a carefully designed

MOSFET for threshold voltage, the source and the body are tied together

internally, making MOSFET a three-terminal device (source, drain, and gate).

6.2 MOS Capacitor

The metal (or polysilicon)–oxide–semiconductor sequence without source

and drain contacts forms an MOS-C capacitor (C is for capacitor not to be

Source

p-type Si substrate

SiO

2

Drain

W

Gate

V

S

V

G

V

D

x

z

y

x = 0 x = L

L

ε

1

ε

t

n

+

n

+

n

+

t

ox

Z

OM

FIGURE 6.1

Basic structure of an n-channel MOSFET with electrons removed from the Si/SiO

2

interface

due to the quantum-connement effect.