Nanoscale Semiconductor Memories

2	Complete Guide to Multiple Upsets in SRAMs Processed in Decananometric CMOS Technologies
Gilles Gasiot and Philippe Roche

CONTENTS

2.1    Introduction

2.2    Details on the Experimental Setup

2.2.1    Note on the Importance of Test Algorithm for Counting Multipl

2.2.2    Test Facility

2.2.2.1    Alpha Source

2.2.2.2    Neutron Facilities

2.2.2.3    Heavy-Ion Facilities

2.2.2.4    Proton Facility

2.2.3    Tested Devices

2.3    Experimental Results

2.3.1    MCU as a Function of Radiation Source

2.3.2    MCU as a Function of Well Engineering: Triple Well Usage

2.3.3    MCU as a Function of Tilt Angle during Heavy Ion Experiments

2.3.4    MCU as a Function of Technology Feature Size

2.3.5    MCU as a Function of Design: Well Tie Density