Nanoscale Semiconductor Memories

3	Radiation Hardened by Design SRAM Strategies for TID and SEE Mitigation
Lawrence T. Clark

CONTENTS

3.1    Chapter Overview

3.1.1    Embedded SRAMs in IC Design

3.1.2    Radiation Space Environment and Effects

3.1.3    Chapter Outline

3.2    Radiation Hardening

3.2.1    Total Ionizing Dose Effects

3.2.2    Single Event Effects in SRAMs

3.3    Radiation Hardening by Design in SRAMs

3.3.1    SRAM Cell Read and Write Margins

3.3.2    Reverse-Body Bias

3.3.3    RHBD SRAM Cell Design

3.3.3.1    Conventional Two-Edged Transistor Cell (Type 1)

3.3.3.2    Annular NMOS-Based SRAM Cell (Type 2)

3.3.3.3    PMOS Access Transistor SRAM Cell (Type 3)

3.3.3.4    Two-Edged NMOS Access Transistor SRAM Cell with Annular Pull-Down Transistors (Type 4)