Nanoscale Semiconductor Memories

5	Concepts of Capacitorless 1T-DRAM and Unified Memory on SOI
Sorin Cristoloveanu and Maryline Bawedin

CONTENTS

5.1    Introduction

5.2    1T-DRAM Operating Mechanisms

5.3    1T-DRAM Architectures

5.3.1    Z-RAM Variants

5.3.2    Fully Depleted 1T-DRAM

5.3.3    1T-DRAMs with Nonconventional MOSFET Architectures

5.3.4    MSDRAM Memory Cell

5.3.5    ARAM Memory Cells

5.3.6    Z2-RAM Memory Cell

5.3.7    Unified Memory

5.4    Conclusions

Acknowledgment

References

5.1    INTRODUCTION

While the scaling of MOS transistors is going on, the miniaturization of the DRAM storage capacitor reaches a critical limit. A novel and responsible strategy consists of attempting to suppress the capacitor. Silicon-on-Insulator (SOI) technology offers the opportunity ...