4.1 Evaluation Methodologies of NoC
This section presents the strategy to evaluate the performance and cost of networks-on-chip (NoCs). In the NoC paradigm, while evaluating the performance of an interconnect infrastructure, its energy consumption profile and silicon area overhead must also be considered, as it can be a significant portion of the overall system-on-chip (SoC) cost budget. It has been reported in the work of Pande et al. (2005) that Scalable, Programmable Integrated Network (SPIN) and octagon network have very high throughput, but their energy consumption and silicon area overhead are much higher than both mesh and butterfly fat tree (BFT). Folded torus shows almost similar ...
