CHAPTER 10 EZchip Architecture, Capabilities, and Applications
EZchip architecture is based on a pipeline of parallel heterogeneous processors, optimized for packet processing according to the various phases we discussed in the theory part of the book. Each processor along the pipeline is equipped with functional units, memory, and internal data buses that support its specific function in the pipeline as a whole.
There are many EZchip network processor types and versions, suited to various applications. They all, however, share the common architecture mentioned before, which will be described in this chapter. The emphasis is on the network processor chip architecture, in terms of features, applications, interfaces, and hardware, whereas the ...
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