Dynamic virtual channel routers with congestion awareness†
Buffer resources are key components of the on-chip router. In this chapter we propose two dynamic virtual channel (VC) structures. First, a dynamically allocated VC architecture with congestion awareness is introduced. All the buffers are shared among VCs, whose structure varies with the traffic condition. At a low rate, this structure extends the VC depth for continual transfers to reduce packet latencies. At a high rate, it dispenses many VCs and avoids congestion situations to improve the throughput. We modify the VC controller and VC allocation modules, and design simple congestion-avoidance logic. Second, we present a novel on-chip network router with a shared ...
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