book

Networks on Chips

by Giovanni De Micheli, Luca Benini, Davide Bertozzi, Israel Cidon, Kees Goossens, Kwanho Kim, Kangmin Lee, Se-Joong Lee, Srinivasan Murali, Hoi-Jun Yoo

August 2006

Intermediate to advanced

408 pages

10h 58m

English

Morgan Kaufmann

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Copyright
The Morgan Kaufmann Series in Systems on Silicon
About the Authors
List of Contributors
1. Networks on Chip
1.1. Why On-Chip Networking?1.2. Technology Trends1.2.1. Signal Integrity1.2.2. Reliability1.2.3. Non-determinism in SoC Modeling and Design1.2.4. Variability, Design Methodologies and NoCs1.3. SoC Objectives and NoC Needs1.3.1. Some Design Examples1.3.2. Distinguishing Characteristics of NoCs1.4. Once Over Lightly1.4.1. NoC Architectures1.4.2. Physical Layer1.4.3. Data-Link Layer1.4.4. Network and Transport Layers1.4.5. Software Layers1.4.6. NoC Design Tools and Design Examples1.5. PerspectivesReferences
2. Network Architecture: Principles and Examples
2.1. Network Architecture2.1.1. Shared-Medium Networks2.1.2. Direct Networks2.1.3. Indirect Networks2.1.4. Hybrid Networks2.2. Network Architectures for On-Chip Realization2.3. Ad Hoc Network Architectures2.4. Component Design for NoCs2.4.1. Switch Design2.4.2. Link Design2.4.3. NI Design2.5. Properties of Network Architectures2.6. SummaryReferences
3. Physical Network Layer
3.1. Interconnection in DSM SoC3.1.1. Interconnection Models3.1.2. Signal Integrity and Noises on the Interconnect3.1.3. Issues in Power and Clock Distribution3.2. High-Performance Signaling3.2.1. High-Speed SignalingVoltage-mode signalingCurrent-mode signalingWave-pipelining3.2.2. Low-Power Interconnection DesignChannel coding to reduce the switching probabilityWire capacitance reducing techniquesLow-swing signalingDriver circuitsReceiver circuitsStatic and dynamic wiresOptimal voltage swingFrequency/voltage scaling3.2.3. SynchronizationClock distribution inside an NoCSynchronizers3.3. Building Blocks3.3.1. Switch DesignSwitch fabricSwitch scheduler3.3.2. Queuing Buffer and Memory Design3.3.3. Size Determination of Physical Transfer unitSize of physical transfer unitOn-chip serializationSerializer/deserializer circuits3.4. SummaryReferences

4. The Data-Link Layer in NoC Design
4.1. Tasks of the Data-Link Layer4.2. On-Chip Communication Reliability4.3. Fault Models for NoCs4.3.1. Bit Error Rate Model4.3.2. New Fault Model Notations4.3.3. Stochastic Failure Model4.4. Principles of Coding Theory4.4.1. Linear Block CodesSyndromesStandard array decodingSyndrome decoding4.4.2. Hamming Codes4.4.3. Cyclic CodesGenerator polynomialBurst errors4.4.4. Cyclic Redundancy Check4.4.5. Implementation of Hamming Codecs4.4.6. Implementation of Cyclic Codecs4.5. The Power-Reliability Trade-Off4.5.1. Conflicting Requirements on Voltage Swing4.5.2. Conflicting Requirements on Switching Activity4.6. Unified Coding Framework4.7. Adaptive Error Protection4.7.1. Self-Calibrating NoCs4.7.2. Coding Adaptation4.8. Data-Link Layer Architecture: Case Studies4.8.1. Micro-Modem4.8.2. Nostrum4.9. On-Chip Stochastic Communication4.10. Link-Level versus End-to-End Error Protection4.11. Flow Control4.11.1. Flow Control Protocols4.12. Performance Exploration4.12.1. Considerations4.13. SummaryReferences
5. Network and Transport Layers in Networks on Chip
5.1. Network and Transport Layers in NoCs5.1.1. Classifying NoC ModelsASICASSP and platformsFPGAsCMPs5.2. NoC QoS5.2.1. Traffic Classes and Service ClassesTraffic classes and service classes in computer networksTraffic classes and service classes in NoCs5.3. NoC TopologyNoC types and topologies5.4. Switching Techniques5.4.1. Circuit SwitchingVirtual channels and virtual circuitsVirtual circuits with multiple buffers per linkVirtual circuits with a single buffer per linkCircuit management5.4.2. Packet SwitchingSAF switchingVCT switchingWH switching5.4.3. Combinations of Different Switching Techniques5.5. NoC Addressing and Routing5.6. NoC Addressing5.6.1. NoC RoutingStatic and dynamic routingDistributed and source routingMinimal and non-minimal routing5.6.2. DeadlockDeadlock avoidance5.6.3. NoC Dynamic Routing Schemes5.7. Congestion Control and Flow Control5.7.1. Congestion ControlCongestion control without resource reservationsCongestion control with resource reservations5.7.2. Flow Control5.7.3. Congestion Control and Flow Control for QoS5.8. SummaryReferences
6. Network Interface Architecture and Design Issues
6.1. NI Services6.1.1. Adaptation ServicesCore interfacingPacketization6.1.2. Clock AdaptationBandwidth and latency guarantees6.1.3. Network ServicesTransactions orderingReliable transactionsFlow control6.1.4. Functional ServicesCache coherenceSecurityLow power6.2. NI Structure6.3. Evolution of Communication Protocols6.3.1. Considerations6.4. Point-to-Point Communication Protocols6.4.1. AXI OverviewAdvanced options6.4.2. OCP OverviewBus bridgeProcessor interfaceMemory subsystemSignals common to each example6.4.3. Bus versus Network SemanticsProgramming modelTransaction orderingAtomic chains of transactionsDeadlockMedia arbitrationDestination name and routingLatencyData formatBuffering and flow control6.5. Latest Advances in Processor Interfaces6.6. The Packetization Stage6.6.1. Hardware–Software ImplementationSoftware library for packetizationOn-core module for packetizingWrapper logic for packetizingComparison6.6.2. Packet Types6.6.3. Impact of Packet Size6.6.4. Impact of Flit Size6.7. End-to-End Flow Control6.8. Packet and Circuit Switching6.9. NI Architecture: The Aethereal Case Study6.9.1. NI Kernel Architecture6.9.2. NI Shell Architecture6.9.3. Network Configuration6.9.4. NI Configuration6.9.5. Implementation6.9.6. NI and the Rest of the System6.10. NI Architecture: The xpipes Case Study6.10.1. The NI and the Rest of the System6.11. NIs for Asynchronous NoCs: The Mango Case Study6.11.1. Implementation Results6.12. SummaryReferences
7. NoC Programming
7.1. Architectural Template7.1.1. Shared Memory MPSIM7.1.2. Message-Oriented Distributed Memory MPSIM7.1.3. Memory Abstraction Implications on Interconnect Architecture7.2. Task-Level Parallel Programming7.2.1. Message PassingMessage-passing implementation in MPSoCsProgramming a message-passing NoC platformMessage-passing performance analysis7.2.2. Shared memoryShared-memory in MPSoCsProgramming a shared-memory NoC platformShared-memory performance analysis7.3. Communication-Exposed Programming7.3.1. Graphical dataflow programming environments7.3.2. Stream LanguagesA case study: StreamIt7.4. Computer-Aided Software Development Tools7.4.1. CompilationCoarse-grain parallelism extraction7.4.2. Testing and debugging7.5. SummaryReferences
8. Design Methodologies and CAD Tool Flows for NoCs
8.1. Network Analysis and Simulation8.1.1. NoC Modeling EnvironmentsThe MPARM environmentNoC emulation8.1.2. Application Traffic Models8.2. Network Synthesis and Optimization8.2.1. NoC Architecture Exploration8.2.2. NoC Instantiation8.3. Design Flows for NoCs8.3.1. NetChipSunmapSunfloorxpipes8.3.2. Æthereal Design Flow8.3.3. Input SpecificationNoC generation and configurationNoC verificationNoC simulation8.4. Tool Kits for Designing Bus-Based Interconnect8.4.1. Silicon Backplane and Sonics Studio8.4.2. STMicroelectronics STBusBasics on the STBusSTBusGenKitThe SLD toolThe SD tool8.4.3. Arteris8.5. SummaryReferences
9. Designs and Implementations of NoC-Based SoCs
9.1. KAIST BONE Series9.1.1. BONE-1: Prototype of On-Chip Network (PROTON)Overall architecturePacket routing schemeOff-chip connectivity9.1.2. BONE-2: Low-Power NoC and Network-in-Package for Multimedia SoC ApplicationsTopology selectionSignal synchronization and serializationLow-swing signaling on global linksCrossbar partial activation techniqueLow-energy coding on on-chip serial linkOperating frequency scalingDesign flow and methodologyChip implementationNetworks-in-packageMeasurements and demonstration of system operationBONE-2 chip summary9.1.3. BONE-3Supply-voltage-dependent reference voltageSelf-calibrating phase differenceAdaptive link bandwidth control9.1.4. FONE: Flexible On-Chip NetworkNoC evaluation platformNoC run-time traffic monitoring systemCase study: portable multimedia systemTarget system descriptionNoC evaluationNoC optimizationFONE platform summary9.2. NoC-Based Experimental Systems9.2.1. Pleiades: Heterogeneous Reconfigurable Processor for Baseband Wireless Application9.2.2. Raw Machine: Scalable Multiprocessor Architecture9.2.3. Multi-Context Network Using Flash-EEPROM Switches and Elastic Interconnects9.3. SummaryReferences

Content preview from Networks on Chips

Chapter 5. Network and Transport Layers in Networks on Chip^[*]

The main goal of the network and transport layers is to support the end-to-end communication between the modules at the specified quality of service (QoS) using a power- and resource-efficient sharing of the interconnect resources. This seemingly simple goal forces the designer to address all classical (and some new) network layer issues in the context of an individual chip design.

In order to define the end-to-end QoS, we need to define the on-chip communication requirements in terms of the module-to-module traffic types, rates, statistical behavior, and predictability. For each such end-to-end flow we also need to define the service it receives such as loss and delay. We also need ...

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Networks on Chips

by Giovanni De Micheli, Luca Benini, Davide Bertozzi, Israel Cidon, Kees Goossens, Kwanho Kim, Kangmin Lee, Se-Joong Lee, Srinivasan Murali, Hoi-Jun Yoo

Chapter 5. Network and Transport Layers in Networks on Chip^[*]

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