Chapter 8. Design Methodologies and CAD Tool Flows for NoCs[*]
Designing networks on chips (NoCs) is a complex process and spans several abstraction levels, ranging from the transaction to the physical levels. Design choices are difficult to make, because most figures of merit of the network depend highly on high-level decisions on architectures and protocols. Yet these decisions can only be validated while considering physical layer measures, such as delays on interconnection links. Thus, potential design closure issues may require designers to explore various configurations with different parameters in the search for those that satisfy the network and overall system specifications. Computer-aided design (CAD) tools are therefore very useful ...
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