CMOS Photonics for High Performance Interconnects
Jason Orcutt, Rajeev Ram and Vladimir Stojanović, Massachusetts Institute of Technology.
12.1 On-Chip Interconnects and Power—A System Architect’s View
Over the last few years, there has been a dramatic shift in microprocessor architecture. Since 2002, uniprocessor performance has increased far more slowly than over the preceding 20 years, due to increasing power consumption, wire delay, and memory latency, as well as diminishing returns from further exploitation of instruction-level parallelism (ILP). Already, in 2006, uniprocessor performance was three times slower than historic trends would have predicted in 2002.
Manufacturers have turned away from ever larger and ever less efficient ...
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