Memory bus speed and width

One of the primary functions of a chipset is to serve as an intermediary between the processor and main memory. The memory controller portion of the chipset has two important duties. First, it reduces load on the processor by performing some memory functions without intervention from the processor, including routine housekeeping chores such as refreshing memory and managing DMA. Second, when the processor reads from or writes to main memory, it does not do so directly. Instead, the memory controller portion of the chipset works as the middleman, accepting data from the processor and transferring it to main memory, or vice versa.

Just as the FSB connects the chipset to the processor, the memory bus connects the chipset to main system memory. The speed and width of the memory bus determine how fast data can be transferred between the chipset and main memory. Unless the memory bus can transfer data at least as fast as the FSB can, the processor may become starved for data. Accordingly, modern chipsets are optimized to provide a fast memory bus. The following two interrelated factors determine throughput:

Memory bus speed

Memory bus speed determines the fastest memory that can be used. For example, a chipset may be designed to support DDR-SDRAM at a maximum memory bus speed of 333 MHz, which means that the memory bus is optimized for DDR333 (PC2700) memory. Another chipset may be designed to use DDR-SDRAM at a maximum memory bus speed of 400 MHz, which means ...

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