CAS Latency

CAS latency is the delay, in clock cycles, between the time the processor requests data from memory and the time the memory makes the first piece of data available to be read. SDR-SDRAM modules may have a CAS latency of 1, 2, or 3. DDR-SDRAM modules have a CAS latency of 2 or 2.5. CAS latency is often abbreviated as CAS or CL. For example, a PC133 module may be labeled CAS2, CAS-2, CAS=2, CL2, CL-2, or CL=2, all of which mean that module has a CAS latency of 2.

Current systems read memory in 32-bit chunks, comprising four 8-bit bytes. CAS latency specifies the number of clock cycles required before the first byte can be read. After that first byte is read, the remaining bytes are read without latency, in one clock cycle each. For example, CL3 memory delivers the first byte after three clock cycles and the other three bytes in one clock cycle each. This memory timing is designated 3-1-1-1 and indicates that six clock cycles (3+1+1+1) are needed to read all four bytes. CL2 memory uses a 2-1-1-1 memory timing, and therefore reads all four bytes in five clock cycles (2+1+1+1). Similarly, CL1 memory uses a 1-1-1-1 memory timing and requires only four clock cycles to complete the read.

On that basis, one might conclude that CL2 memory is 16.7% faster than CL3 memory and CL1 memory is 33.3% faster than CL3, which is a substantial difference. In fact, that differential holds only for single 32-bit reads, whereas most reads are streaming. During streaming reads, each 32-bit ...

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